Semiconductor devices are essentially switching devices. The output drivers within these devices create an intermittent current flow through the circuit's bond wires and associated conductive traces. As such, voltage surges develop with the potential for creating logic errors. Other logic damaging transient voltages are caused by voltage fluctuations along the power line as well as the interaction of other circuit components within the system.
In order to abate the potential effect of transient voltages, decoupling capacitors are commonly employed. Referring to FIG. 1, a series of decoupling capacitors 20 are connected between a ground bus (V.sub.SS bus) 16 and a power bus (V.sub.cc bus) 14 of a semiconductor chip 10. The capacitance value of each decoupling capacitor 20 is high relatively, for example on the order of 1.6 nF to 1.8 nF, when compared with the values of the capacitors employed directly by semiconductor chip 10, for example in the range of 10 fF to 20 fF.
Several problems have arisen with regards to the failing of one or more decoupling capacitors. Decoupling capacitors are fabricated by sandwiching a dielectric layer between two conductive plates. However, in the event that a decoupling capacitor's dielectric layer fails, a short may arise, potentially destroying the semiconductor chip.
What is needed is a technique for disconnecting decoupling capacitors which have failed. Ideally, the step of disconnecting must avoid additional manufacturing and labor costs. Thus, a circuit design solution incorporated into current chip manufacturing processes is preferable. Additionally, the total chip decoupling capacitance must not be significantly altered in the event of a capacitor failure. Further, significant additional chip area must not be necessitated for disconnecting failed decoupling capacitors beyond the area required for conventional decoupling capacitors.
One solution to the shorting problem for decoupling capacitors has been proposed in U.S. Pat. No. 4,879,631 assigned to Micron Technology, Incorporated. The invention teaches placing multiple pairs of decoupling capacitors in series between the ground and power buses to dramatically reduce the possibility of destroying the semiconductor chip. However, the proposed approach of coupling two capacitors in series requires much more charge storage area to achieve the equivalent capacitance of a single capacitor. As utilizing space on semiconductor chips is costly, such a scheme is not always a feasible alternative for providing a decoupling capacitor system on the chip.
In another solution, a multitude of decoupling capacitors are connected in parallel between a V.sub.cc bus and a V.sub.ss bus of the semiconductor chip. At least one plate of each decoupling capacitor is connected to the bus by means of an electrically fusible link. The dimensions and characteristics of the electrically fusible link are such that, in the event that the decoupling capacitor associated therewith fails, the electrically fusible link will blow, thereby forming an open circuit and decoupling the capacitor from the remainder of the semiconductor chip. Thus, the decoupling of the electrically fusible link is dependent on internal stimulus in the chip's interaction, i.e, the generation of sufficient current to blow the fuse link.
Difficulties have also arisen in feasibly manufacturing an electrically fusible link. Further, the materials employed to form the electrically fusible link have shown poor sensitivity, tolerances, and a high rate of false triggers in disconnecting the decoupling capacitors. Under this approach, as no sensing mechanism is necessary to ascertain whether a decoupling capacitor has failed, several properly functioning decoupling capacitors can be accidentally disconnected from the bus. Further, by relying on an electrically fusible link, a decoupling capacitor can be disconnected from the chip at any time.